Sun, 15 Nov 2026 11:18:54 UTC Log in
VHDL to Verilog translator 62.97 KB built 2026-10-18 04:29:24 GMT

Description

vhd2vl is a VHDL to Verilog translation program. It targets the translation of synthetisable RTL. While far from complete it supports a useful subset of VHDL, sufficient for complex designs.

Dependencies

8 total
Requires7
  • bison
  • flex
  • flex-devel
  • gcc
  • make
  • rpmlib(CompressedFileNames) <= 3.0.4-1
  • rpmlib(FileDigests) <= 4.6.0-1
Provides1
  • vhd2vl = 2.5-29.fc45
ObsoletesNo Obsoletes
ConflictsNo Conflicts
RecommendsNo Recommends
SuggestsNo Suggests
SupplementsNo Supplements
EnhancesNo Enhances

Files

2
Files 1–2 of 2

Component of

buildroots that installed this RPM

No Buildroots