Mon, 09 Nov 2026 01:46:49 UTC Log in
Complete grammar for parsing Verilog code using perl 149.02 KB built 2026-10-16 20:22:25 GMT

Description

This module defines the complete grammar needed to parse any Verilog code. By overloading this grammar, it is possible to easily create perl scripts which run through Verilog code and perform specific functions.

Dependencies

19 total
Requires15
  • /usr/bin/perl
  • perl(:VERSION) >= 5.0.0
  • perl(Benchmark)
  • perl(Data::Dumper)
  • perl(Hardware::Verilog::Hierarchy)
  • perl(Hardware::Verilog::Parser)
  • perl(Hardware::Verilog::StdLogic)
  • perl(Parse::RecDescent)
  • perl(strict)
  • perl(vars)
  • perl-libs
  • rpmlib(CompressedFileNames) <= 3.0.4-1
  • rpmlib(FileDigests) <= 4.6.0-1
  • rpmlib(PayloadFilesHavePrefix) <= 4.0-1
  • rpmlib(PayloadIsZstd) <= 5.4.18-1
Provides4
  • perl(Hardware::Verilog::Hierarchy) = 0.03
  • perl(Hardware::Verilog::Parser) = 0.13
  • perl(Hardware::Verilog::StdLogic) = 0.03
  • perl-Hardware-Verilog-Parser = 0.13-49.fc45
ObsoletesNo Obsoletes
ConflictsNo Conflicts
RecommendsNo Recommends
SuggestsNo Suggests
SupplementsNo Supplements
EnhancesNo Enhances

Files

13
Files 1–13 of 13

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