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Complete grammar for parsing Verilog code using perl 44.64 KB built 2026-10-16 20:22:16 GMT

Description

This module defines the complete grammar needed to parse any Verilog code. By overloading this grammar, it is possible to easily create perl scripts which run through Verilog code and perform specific functions.

Dependencies

13 total
Requires12
  • findutils
  • make
  • perl(Benchmark)
  • perl(Data::Dumper)
  • perl(ExtUtils::MakeMaker)
  • perl(Parse::RecDescent)
  • perl(strict)
  • perl(vars)
  • perl-generators
  • perl-interpreter
  • rpmlib(CompressedFileNames) <= 3.0.4-1
  • rpmlib(FileDigests) <= 4.6.0-1
Provides1
  • perl-Hardware-Verilog-Parser = 0.13-49.fc45
ObsoletesNo Obsoletes
ConflictsNo Conflicts
RecommendsNo Recommends
SuggestsNo Suggests
SupplementsNo Supplements
EnhancesNo Enhances

Files

5
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